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Integrated Circuit Systems, Inc.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
FEATURES
* One differential 3.3V LVPECL output * One CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum clock input frequency: 1GHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input * Part-to-part skew: 300ps (maximum) * Propagation delay: 2.1ns (maximum) * LVPECL mode operating voltage supply range: VCC = 3.0V to 3.465V, VEE = 0V * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS87354I is a high performance /4//5 Differential-to-3.3V LVPECL Clock Generator HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The ICS87354I is characterized to operate from a 3.3V power supply. Guaranteed output and part-topart skew characteristics make the ICS87354I ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
CLK nCLK R /4 /5 0 1 Q nQ
PIN ASSIGNMENT
CLK nCLK MR F_SEL 1 2 3 4 8 7 6 5 Vcc Q nQ VEE
MR
ICS87354I
8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View
F_SEL
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Integrated Circuit Systems, Inc.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
Type Input Input Input Pullup Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 Name CLK nCLK MR Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output (Q) to go low and the inver ted output Pulldown (nQ) to go high. When logic LOW, the internal dividers and the output are enabled. LVCMOS / LVTTL interface levels. See Table 3. Selects divider value for Q, nQ outputs as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. Positive supply pin.
4 5 6, 7 8
F_SEL VEE Q, nQ VCC
Input Power Output Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3. FUNCTION TABLE
MR 1 0 0 F_SEL X 0 1 Divide Value Reset: Q output low, nQ output high /4 /5
CLK
tRR
MR
Q
FIGURE 1. TIMING DIAGRAM
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Integrated Circuit Systems, Inc.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 3.465V, VEE = 0, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.465 104 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.0V TO 3.465V, VEE = 0, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH IIL Input High Voltage Input Low Voltage Input High Current Input Low Current MR, F_SEL MR, F_SEL VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 15 0 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.0V TO 3.465V, VEE = 0, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
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Integrated Circuit Systems, Inc.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.0V TO 3.465V, VEE = 0, TA = -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.0V TO 3.465V, VEE = 0, TA = -40C TO 85C
Symbol fCLK Parameter Clock Input Frequency Propagation Delay; CLK to Q (Dif) NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Reset Recovery Time Minimum Input Pulse Width Output Rise/Fall Time Test Conditions Minimum Typical Maximum 1 1.7 2.1 300 400 CLK 20% to 80% 550 300 600 52 Units GHz ns ps ps ps ps %
tPD tsk(pp)
tRR tPW t R / tF
odc Output Duty Cycle 48 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JUNE 27, 2005
Integrated Circuit Systems, Inc.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
V CC
Qx
SCOPE
V CC
nCLK
LVPECL
VEE
nQx
V CLK
PP
Cross Points
V
CMR
-1.0V to -1.465V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1 nQx Qx PART 2 nQy Qy
tsk(pp)
nCLK CLK nQ Q
tPD
PART-TO-PART SKEW
PROPAGATION DELAY
nQ 80% Clock Outputs 80% VSW I N G 20% tR tF
odc =
Q
t PW
t
PERIOD
20%
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
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OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A JUNE 27, 2005
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ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUT
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
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FIGURE 2B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc. DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL HiPerClockS Input R1 50 R2 50 Zo = 50 Ohm nCLK HiPerClockS Input CLK
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A JUNE 27, 2005
Integrated Circuit Systems, Inc.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87354I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS87354I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 104mA = 360mW Power (outputs)MAX = 3.465mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 360mW + 30mW = 390mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.390W * 103.3C/W = 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A JUNE 27, 2005
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ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87354I is: 1745
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ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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ICS87354I
/4//5 DIFFERENTIAL-TO3.3V LVPECL CLOCK GENERATOR
Marking 87354AMI 87354AMI 87354AIL 87354AIL Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87354AMI ICS87354AMIT ICS87354AMILF ICS87354AMILFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87354AMI
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